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this is information on a product in full production. october 2012 doc id 13103 rev 13 1/35 1 l4995 5v, 500ma low drop voltage regulator datasheet ? production data features operating dc supply voltage range 5.6v to 31v low dropout voltage low quiescent current consumption reset circuit sensing of output voltage down to 1v programmable reset pulse delay with external capacitor programmable watchdog (a) timer with external capacitor thermal shutdown and short circuit protection wide temperature range (t j = -40c to 150c) enable (a) input for enabling/disabling the voltage regulator description l4995 is a family of monolithic integrated 5 v voltage regulators with a low drop voltage at currents of up to 500 ma, available in both 12 and 24 pin packages. the output voltage regulating element consists of a p-channel mos and regulation is performed regardless of input voltage transients of up to 40v. the high precision of the output voltage is obtained using a pre-trimmed reference voltage. the l4995 family is protected against short circuit and overtemperature protection switches off the devices in the case of extremely high power dissipation. the l4995 integrates the watchdog, enable and externally programmable reset circuits. the l4995a features the externally programmable reset and enable. finally the l4995r features the externally programmable reset. the combination of such features makes this device particularly flexible and suitable to supply microprocessor systems in automotive applications. max dc supply voltage v s 40v max output voltage tolerance v 0 +/-2% max dropout voltage v dp 500mv output current i 0 500ma quiescent current i qn 3a (1) 1. typical value with regulator disabled a. watchdog and enable facilities are available according to device summary table. powersso- 12 powersso-24 table 1. device summary package order codes tube tape and reel powersso-12 (exposed pad) l4995j - l4995aj - l4995rj l4995jtr - l4995ajtr - l4995rjtr powersso-24 (exposed pad) l4995k - l4995ak - l4995rk l4995ktr - l4995aktr - l4995rktr p/n watchdog reset enable l4995j - l4995k x x x l4995aj - l4995ak - x x l4995rj - l4995rk - x - www.st.com
contents l4995 2/35 doc id 13103 rev 13 contents 1 block diagrams and pins descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 test circuit and waveforms plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.1 load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 powersso-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 powersso-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2 powersso-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3 powersso-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4 powersso-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
l4995 list of tables doc id 13103 rev 13 3/35 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pins descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7. watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 8. enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 9. powersso-12 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. powersso-24 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. powersso-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12. powersso-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
list of figures l4995 4/35 doc id 13103 rev 13 list of figures figure 1. block diagram of l4995 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. block diagram of l4995a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. block diagram of l4995r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. pins configurations (l4995) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. output voltage vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. output voltage vs v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. drop voltage vs output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. current consumption vs output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 figure 9. current consumption vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 figure 10. current limitation vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11. current limitation vs input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 12. short circuit current vs input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 13. output voltage vs enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 14. v en_high vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 15. v en_low vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 16. v rhth vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 17. v rlth vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 18. v whth vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 19. v wlth vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 20. i cr and i cwc vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 21. i dr and i cwd vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 22. t wop vs t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 23. psrr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 24. load regulation test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 25. maximum load variation response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 26. l4995 application schematic (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 27. stability region (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 28. behavior of output current versus regulated voltage v o . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 29. reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 30. watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 31. powersso-12 pc board (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 32. rthj-amb vs pcb copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 20 figure 33. powersso-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 21 figure 34. thermal fitting model of vreg in powersso-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 35. powersso-24 pc board (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 36. rthj-amb vs pcb copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 23 figure 37. powersso-24 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 24 figure 38. thermal fitting model of v reg in powersso-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 39. powersso-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 40. powersso-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 41. powersso-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 42. powersso-12 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 43. powerss0-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 44. powersso-24 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
l4995 block diagrams and pins descriptions doc id 13103 rev 13 5/35 1 block diagrams and pins descriptions figure 1. block diagram of l4995 figure 2. block diagram of l4995a 9rv 9r 9v (q 9fu :l 5hv 9fz 6 3 6%n 6cw 6wi 6cr 6 2es 6o )s ) %n )c w )o '.$ zdwfkgrj 9rowdjh 5hihu hqfh /rz9rowdjh 5h vh w 6wduwxs p9 b 9 ("1(.4 9r v 9r 9v (q 9fu 5h v 6 3 6%n 6cr 6 2es 6o )s ) %n )o '.$ 9rowdjh 5h i h u h q f h /r z9rowdjh 5hvhw 6wduwxs p9 b 9 '!0'-3
block diagrams and pins descriptions l4995 6/35 doc id 13103 rev 13 figure 3. block diagram of l4995r table 2. pins descriptions pin name powersso-12 pin # powersso-24 pin # function e n 1 13, 14, 15 enable input (l4995 and l4996a only, otherwise not connected). if high regulator, watchdog and reset are operating. if low regulator, watchdog and reset are shutdown. connect to vs if not used. nc 2, 4, 8 3, 5, 6, 9, 11 not connected. gnd 3 16, 17, 18 ground reference. -tabtab, 1, 12 substrate of the chip: connect the pins or the tab to gnd. r es 5 19, 20, 21 reset output. it is pulled down when output voltage goes below v o_th or frequency at wi is too low. leave floating if not used. v cr 6 22, 23, 24 reset timing adjust. a capacitor between v cr pin and gnd. sets the reset delay time (trd). leave floating if reset is not used. v cw 72 watchdog timer adjust (l4995 only, otherwise not connected). a capacitor between v cw pin and gnd. sets the time response of the watchdog monitor. 9rv 9r 9v 9fu 5hv 6 3 6%n 6cr 6 2es 6o )s )o '.$ 9rowdjh 5hi huhqfh /r z9rowdjh 5hv hw 6wduwxs p9 b 9 '!0'-3
l4995 block diagrams and pins descriptions doc id 13103 rev 13 7/35 figure 4. pins configurations (l4995) w i 94 watchdog input (l4995 only, otherwise not connected). if the frequency at this input pin is too low, the reset output is activated. v os 10 7 regulator voltage output sensing. v o 11 8 5 voltage regulator output. block to ground with a capacitor >100nf (needed for regulator stability). v s 12 10 supply voltage. block to ground directly at v s pin with a ceramic capacitor (e.g. 200nf). table 2. pins descriptions (continued) pin name powersso-12 pin # powersso-24 pin # function 4!"substrate 4!"substrate su b s t ra t e substrate '!0'-3
electrical specifications l4995 8/35 doc id 13103 rev 13 2 electrical specifications 2.1 absolute maximum ratings stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 3. absolute maximum ratings symbol parameter value unit v vsdc dc supply voltage - 0.3 to 40 v i vsdc input current internally limited v vo (1) 1. using the typical application schematic with cout= 10 f and iout=0 a, when the regulator is switched-on, an overshoot exceeding 6 v could o ccur.this behavior does not impact the reliability of the regulator. dc output voltage - 0.3 to 6 v i vo dc output current internally limited v wi watchdog input voltage -0.3 to v vo + 0.3 v v od r es output voltage -0.3 to v vo + 0.3 v i od r es output current internally limited v cr v cr voltage - 0.3 to v vo + 0.3 v v cw watchdog delay voltage - 0.3 to v vo + 0.3 v v en enable input - 0.3 to v vsdc +0.3 v t j junction temperature - 40 to 150 c v esd esd voltage level (hbm-mil std 883c) 2 kv v esd esd voltage level (cdm aec-q100-011) 750 v
l4995 electrical specifications doc id 13103 rev 13 9/35 2.2 thermal data for details, please refer to section 4.1: powersso-12 thermal data and section 4.2: powersso-24 thermal data . mm 2.3 electrical characteristics values specified in this section are for v s = 5.6v to 31v, t j = -40 c to +150 c unless otherwise stated. table 4. thermal data (1) 1. the values quoted are for pcb 77mm x 86mm x 1.6mm, fr4, double layer; copper thickness 0.070mm copper area 3cm2 thermal vias, thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, cu thickness on vias 0.025 mm. symbol parameter value unit r thj-case thermal resistance junction to case: powersso-12 powersso-24 5 4 k/w k/w r thj-amb thermal resistance junction to ambient: powersso-12 powersso-24 52 38 k/w k/w table 5. general pin symbol parameter test condition min. typ. max. unit v o v o_ref output voltage v s = 5.6 to 31v i o = 0 to 500ma 4.95.005.1 v v o i short short circuit current v s = 13.5v (1) 550 800 1050 ma v o i lim (2) output current limitation v s = 13.5v (1) 600 900 1250 ma v s , v o v line line regulation voltage v s = 5.6 to 31v i o = 0 to 500ma 25 mv v o v load load regulation voltage i o = 0 to 500ma 25 mv v s , v o v dp (3) drop voltage i o = 400ma 270 500 mv v s , v o svr ripple rejection f r = 100 hz (4) 55 db v s , v o i qs current consumption with regulator disabled v s = 13.5v, e n = low 310 a v s , v o i qn_1 current consumption with regulator enabled v s = 13.5v, i o < 1ma, 90 160 a v s , v o i qn_50 current consumption with regulator enabled v s = 13.5v, i o = 50ma, 290 400 a
electrical specifications l4995 10/35 doc id 13103 rev 13 v s , v o i qn_150 current consumption with regulator enabled v s = 13.5v, i o = 150ma, 740 1000 a v s , v o i qn_250 current consumption with regulator enabled v s = 13.5v, i o = 250ma, 11.4ma v s , v o i qn_500 current consumption with regulator enabled v s = 13.5v, i o = 500ma, 2.1 2.7 ma t w thermal protection temperature 150 190 c t w_hy thermal protection temperature hysteresis 10 c 1. see figure 28 . 2. measured output current when the output voltage has dropped 100mv from its nominal value obtained at vs=13.5v and i o = 250ma . 3. vs-v o measured when the output voltage has dropped 100mv from its nominal value obtained at vs=13.5v and i o = 250ma . 4. guaranteed by design. table 6. reset pin symbol parameter test condition min. typ. max. unit r es v res_l reset output low voltage r ext = 5k to v o , v o > 1v 0.4 v r es i res_lkg reset output high leakage current v res = 5v 1 a r es r res pull up internal resistance (versus v o ) 10 20 40 k r es v o_th v o out of regulation threshold v s = 5.6 to 31v i o = 1 to 500ma 6% 8% 10% below v o_ref v cr v rlth reset delay circuit low threshold v s = 13.5v 10% 13% 16% v o_ref v cr v rhth reset delay circuit high threshold v s =13.5v 44% 47% 50% v o_ref v cr i cr charge current v s = 13.5v 8 15 30 a v cr i dr discharge current v s = 13.5v 8 15 30 a r es t rr reset reaction time (1) 1. when v o becomes lower than 4v, the reset reaction time decreases down to 2s assuring a faster reset condition in this particular case. v o = v o_ th -100mv 100 250 700 s r es t rd reset delay time v s = 13.5v, c tr = 47nf 12 33 73 ms table 5. general (continued) pin symbol parameter test condition min. typ. max. unit
l4995 electrical specifications doc id 13103 rev 13 11/35 table 7. watchdog pin symbol parameter test condition min. typ. max. unit w i vih input high voltage v s = 13.5v 3.5 v w i vil input low voltage v s = 13.5v 1.5 v w i vih input hysteresis v s = 13.5v 500 mv w i i wi pull down current v s = 13.5v v wi = 3.5v 610 a v cw v wlth low threshold v s = 13.5v 10% 13% 16% v o_ref v cw v whth high threshold v s = 13.5v 44% 47% 50% v o_ref v cw i cwc charge current v s = 13.5v, v cw = 0.1v 51020 a v cw i cwd discharge current v s = 13.5v, v cw = 2.5v 1.25 2.5 5 a v cw t wop watchdog period v s = 13.5v, c tw = 47nf 20 40 80 ms r es t wol watchdog output low time v s = 13.5v, c tw = 47nf 4816ms table 8. enable pin symbol parameter test condition min. typ. max. unit e n v en_low e n input low voltage 1 v e n v en_high e n input high voltage 3 v e n v en_hyst e n input hysteresis 830 mv e n i en pull down current v s = 13.5v 10 18 a
electrical specifications l4995 12/35 doc id 13103 rev 13 2.4 electrical characteristics curves figure 5. output voltage vs t j figure 6. output voltage vs v s figure 7. drop voltage vs output current figure 8. current consumption vs output current figure 9. current consumption vs input voltage figure 10. current limitation vs t j 4j?# 6o?ref6 6s6 ) m! '!0'-3 6s6 6o?ref6 ) m! 4j?# '!0'-3 )om! 6dp6 4j?# 4j?# '!0'-3 )om! )qn?! 6s6 4j?# %n (igh '!0'-3 6s6 )qn?! 4j?# %n(igh )om! )om! )om! )om! '!0'-3 4j?# )limm! 6s6 '!0'-3
l4995 electrical specifications doc id 13103 rev 13 13/35 figure 11. current limitation vs input voltage figure 12. short circuit current vs input voltage e figure 13. output voltage vs enable voltage figure 14. v en_high vs t j figure 15. v en_low vs t j figure 16. v rhth vs t j 6s6 )limm! 4j?# 4j?# '!0'-3 6s6 )shortm! 4j?# 4j?# '!0'-3 6e n 6 6o6 '!0'-3 4j?# 6en?high6 6s6to6 '!0'-3 4j?# 6en?low6 6s6to6 '!0'-3 4j?# 6rhth6o?ref 6s6to6 '!0'-3
electrical specifications l4995 14/35 doc id 13103 rev 13 figure 17. v rlth vs t j figure 18. v whth vs t j figure 19. v wlth vs t j figure 20. i cr and i cwc vs t j figure 21. i dr and i cwd vs t j figure 22. t wop vs t j 4j?# 6rlth6o?ref 6s6to6 '!0'-3 4j?# 6whth6o?ref 6s6to6 '!0'-3 4j?# 6wlth6o?ref 6s6to6 '!0'-3 4j?# )cr)cwc?! 6s6to6 6cw6 )cr )cwc '!0'-3 4j?# )dr)cwd?! 6s6to6 6cw6 )dr )cwd '!0'-3 4j?# 4wop ms 6s6to6 #tw n& '!0'-3
l4995 electrical specifications doc id 13103 rev 13 15/35 2.5 test circuit and waveforms plot 2.5.1 load regulation figure 24. load regulation test circuit figure 23. psrr 0 , 0 0 1 0 , 0 0 2 0 , 0 0 3 0 , 0 0 4 0 , 0 0 5 0 , 0 0 6 0 , 0 0 7 0 , 0 0 8 0 , 0 0 0 , 1 0 1 , 0 0 1 0 , 0 0 10 1 0 0 , 0 0 1 0 0 0 , 0 0 1 0 0 00 0 0 , 0 0 c 0 = 4.7 f = 4 . 7 f gapgm s 0007 3 frequency [khz] p s rr [db] '!0'-3
electrical specifications l4995 16/35 doc id 13103 rev 13 figure 25. maximum load variation response 0,00e+00 5,00e-05 1,00e-04 1,50e-04 2,00e-04 2,50e-04 3 ,00e-04 3 ,50e-04 4,00e-04 time [s] v 0 [ 1v / div ] i 0 [ 200ma / div ] gapgms00081
l4995 application information doc id 13103 rev 13 17/35 3 application information figure 26. l4995 application schematic (1) 1. the input capacitor cs > 200nf is necessary for the smoothing of line disturbances. the output capacitor c01 > 100nf is necessary for the stability of the regulation loop. in order to dampen output voltage oscillations during high load current surges, it is recommended an additi onal electrolytic capacitor c02 > 10f to be placed at the output pin. figure 27. stability region (1) 1. the curve which describes the minimum esr is deriv ed from characterization data on the regulator with connected ceramic capacitors which feature low esr va lues (at 100 khz). any capacitor with further lower esr than the given plot value must be evaluated in each and every case. 6o s 6o #o watchdog 6s 6i 7i 6c w 6c r #tr #t w 2es gn d 6oltage 2eference ,ow6oltage 2eset 3tartup m6 ? 6 %n #o 6o s 6o #o watchdog 6s 6i 7i 6c w 6c r #tr #t w 2es gn d 6oltage 2eference ,ow6oltage 2eset 3tartup m6 ? 6 %n #o '!0'-3 0.001 0.01 0.1 1 10 100 0.5 5 101520253035404550 co (uf) esr (ohm) esr min esr max unstable region stability region undefined region
application information l4995 18/35 doc id 13103 rev 13 3.1 voltage regulator voltage regulator uses a p-channel transistor as a regulating element. with this structure, very low dropout voltage at current up to 500ma is obtained. the output voltage is regulated up to transient input supply voltage of 40v. no functional interruption due to over-voltage pulses is generated. a short circuit protection to gnd is provided. the voltage regulator is active when e n is high. figure 28. behavior of output current versus regulated voltage v o 3.2 reset the reset circuit supervises the output voltage v o . the v o_th reset threshold is defined with the in-ternal reference voltage and a resistor output divider. if the output voltage becomes lower than v o_th then r es goes low with a reaction time t rr . the reset low signal is guaranteed for an output voltage v o greater than 1v. when the output voltage becomes higher than v o_th then r es goes high with a delay t rd . this delay is obtained by an internal oscillator. the oscillator period is given by: equation 1 t osc = [(v rhth -v rlth ) x c tr ] / i cr + [(v rhth -v rlth ) x c tr ] / i dr where: i cr :is an internally generated charge current i dr :is an internally generated discharge current v rhth , v rlth :are two voltages defined with the output voltage and a resistor output divider c tr :is an external capacitance. t rd is given by: equation 2 t rd = (v rhth x c tr )/i cr + 3 x t osc vo vo_ref iout ishort ilim
l4995 application information doc id 13103 rev 13 19/35 reset is active when e n is high. figure 29. reset timing diagram 3.3 watchdog a connected microcontroller is monitored by the watchdog input w i . if pulses are missing, the reset output pin is set to low. the pulse sequence time can be set within a wide range with the external capacitor, c tw . the watchdog circuit discharges the capacitor c tw , with the constant current icwd. if the lower threshold v wlth is reached, a watchdog reset is generated. to prevent this the microcontroller must generate a positive edge during the discharge of the capacitor before the voltage has reached the threshold v wlth . in order to calculate the minimum time t, during which the micro-controller must output the positive edge, the following equation can be used: equation 3 (v whth -v wlth ) x c tw = i cwd x t every w i positive edge switches the current source from discharging to charging. the same happens when the lower threshold is reached. when the voltage reaches the upper threshold, v whth , the current switches from charging to discharging. the result is a saw-tooth voltage at the watchdog timer capacitor c tw . figure 30. watchdog timing diagram trr < trr trd to s c vrhth vrlth re s vcr vo wi vo u t_th trr < trr trd to s c vrhth vrlth re s vcr vo wi vo u t_th gapgm s 00077 : l 9 fz 5 hv 9 zkwk 9 zowk 7 zrs 7 zro : l 9 fz 5 hv 9 zkwk 9 zowk 7 zrs 7 zro '!0'-3
package and pcb thermal data l4995 20/35 doc id 13103 rev 13 4 package and pcb thermal data 4.1 powersso-12 thermal data figure 31. powersso-12 pc board (1) 1. layout condition of r th and z th measurements (pcb: double layer, thermal vias, fr4 area= 77mm x 86mm,pcb thickness=1.6mm, cu thickness=70 m (front and back side) thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, cu thickness on vias 0.025 mm, footprint dimension 4.1 mm x 6.5 mm). figure 32. r thj-amb vs pcb copper area in open box free air condition ("1($'5 4 0 4 5 5 0 5 5 6 0 6 5 7 0 0 2 4 6 8 1 0 r t h j _a _ a m b ( c / w ) p c b c u h ea e a t s i n k a r ea e a ( c m ^ 2 ) gapgm s 000 8 2
l4995 package and pcb thermal data doc id 13103 rev 13 21/35 figure 33. powersso-12 thermal impedance junction ambient single pulse equation 4: pulse calculation formula where = t p /t figure 34. thermal fitting model of vreg in powersso-12 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100 1000 time ( s) zth ( c/ w) footprint 8 cm 2 2 cm 2 z th r th z thtp 1 ? () + ? = '!0'-3
package and pcb thermal data l4995 22/35 doc id 13103 rev 13 table 9. powersso-12 thermal parameter area/island (cm 2 )footprint28 r1 (c/w) 0.45 r2 (c/w) 1.79 r3 (c/w) 7 r4 (c/w) 10 10 9 r5 (c/w) 22 15 10 r6 (c/w) 26 20 15 c1 (w.s/c) 0.001 c2 (w.s/c) 0.0022 c3 (w.s/c) 0.05 c4 (w.s/c) 0.2 0.1 0.1 c5 (w.s/c) 0.27 0.8 1 c6 (w.s/c) 3 6 9
l4995 package and pcb thermal data doc id 13103 rev 13 23/35 4.2 powersso-24 thermal data figure 35. powersso-24 pc board (1) 1. layout condition of r th and z th measurements (pcb: double layer, thermal vias, fr4 area= 77mm x 86mm,pcb thickness=1.6mm, cu thickness=70 m (front and back side) thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, cu thickness on vias 0.025 mm, footprint dimension 4.1 mm x 6.5 mm). figure 36. r thj-amb vs pcb copper area in open box free air condition gapgcft00418 57 + m b d p e ? & : '!0'-3 3&%&xkhdwvlqnduhdfpa
package and pcb thermal data l4995 24/35 doc id 13103 rev 13 figure 37. powersso-24 thermal impedance junction ambient single pulse equation 5: pulse calculation formula where = t p /t figure 38. thermal fitting model of v reg in powersso-24 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100 1000 time ( s) zth (c/ w) footprint 8 cm 2 2 cm 2 z th r th z thtp 1 ? () + ? = '!0'-3
l4995 package and pcb thermal data doc id 13103 rev 13 25/35 table 10. powersso-24 thermal parameter area/island (cm 2 )footprint28 r1 (c/w) 0.45 r2 (c/w) 1.79 r3 (c/w) 6 r4 (c/w) 7.7 r5 (c/w) 9 9 8 r6 (c/w) 28 17 10 c1 (w.s/c) 0.001 c2 (w.s/c) 0.0022 c3 (w.s/c) 0.025 c4 (w.s/c) 0.75 c5 (w.s/c) 1 4 9 c6 (w.s/c) 2.2 5 17
package and packing information l4995 26/35 doc id 13103 rev 13 5 package and packing information 5.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 39. powersso-12 package dimensions
l4995 package and packing information doc id 13103 rev 13 27/35 table 11. powersso-12 mechanical data symbol millimeters min. typ. max. a 1.250 1.620 a1 0.000 0.100 a2 1.100 1.650 b 0.230 0.410 c 0.190 0.250 d 4.800 5.000 e 3.800 4.000 e0.800 h 5.800 6.200 h 0.250 0.500 l 0.400 1.270 k0o 8o x 2.200 2.800 y 2.900 3.500 ddd 0.100
package and packing information l4995 28/35 doc id 13103 rev 13 5.2 powersso-24 mechanical data figure 40. powersso-24 package dimensions ("1($'5
l4995 package and packing information doc id 13103 rev 13 29/35 table 12. powersso-24 mechanical data (1)(2) 1. no intrusion allowed inwards the leads. 2. flash or bleeds on exposed die pad shall not exceed 0.4 mm per side symbol millimeters min. typ. max. a 2.45 a2 2.15 2.35 a1 0 0.10 b 0.33 0.51 c 0.23 0.32 d (3) 3. ?d and e? do not include mold flash or protusions. mold flash or protusions shall not exceed 0.15 mm. 10.10 10.50 e (3) 7.40 7.60 e0.8 e3 8.8 f2.3 g 0.1 g1 0.06 h10.1 10.5 h 0.4 k0 8 l 0.55 0.85 o1.2 q0.8 s2.9 t3.65 u1 n 10o x4.1 4.7 y 6.5 4.9 (4) 4. variations for small window leadframe option. 7.1 5.5 (4)
package and packing information l4995 30/35 doc id 13103 rev 13 5.3 powersso-12 packing information figure 41. powersso-12 tube shipment (no suffix) figure 42. powersso-12 tape and reel shipment (suffix ?tr?) all dimensions are in mm. base q.ty 100 bulk q.ty 2000 tube length ( 0.5) 532 a1.85 b6.75 c ( 0.1) 0.6 a c b base q.ty 2500 bulk q.ty 2500 a (max) 330 b (min) 1.5 c ( 0.2) 13 f20.2 g (+ 2 / -0) 12.4 n (min) 60 t (max) 18.4 reel dimensions tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 12 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.05) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.1) 5.5 compartment depth k (max) 4.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed
l4995 package and packing information doc id 13103 rev 13 31/35 5.4 powersso-24 packing information figure 43. powerss0-24 tube shipment (no suffix) figure 44. powersso-24 tape and reel shipment (suffix ?tr?) a c b gapgcft00002 %dvh4w\ %xo n4w\ $pd[ %plq &? ) * 1plq 7p d[ 5h h o g l p h q vl r q v 7dshglphqvlrqv !ccordingto%lectronic)ndustries!ssociation %)! 3tandardrev!&eb !lldimensionsareinmm 7dsh zlgwk : 7ds h+r o h6s dfl q j 3? &r psrqhqw6sdflq j3 +roh'ldphwhu '? +r oh'ldphwhu 'plq +r oh3rvlwlrq )? &rpsduwphqw'hswk .pd[ +r oh6sdflqj 3? 4o p cover tap e %nd 3ta rt .ocomponents .ocomponents #omponents mmmin mmmin %m ptycomponentspockets saledwithcovertape 5se rdirectionoffeed ("1($'5
revision history l4995 32/35 doc id 13103 rev 13 6 revision history table 13. document revision history date revision changes 26-may-2006 1 initial release. 05-jan-2007 2 l4995a and l4995r versions added: features section updated and table added. ta bl e 1 updated. table 5: general , watchdog iwi entry updated. figure 2: block diagram of l4995a and figure 3: block diagram of l4995r added. table 2: pins descriptions updated. table 4: thermal data updated. list of tables and list of figures added. packaging information provided in new format. table 11: powersso-12 mechanical data x and y values updated. some sections reformatted for clarity. new disclaimer added. 18-may-2007 3 updated table 2: pins descriptions . updated figure 4: pins configurations (l4995) . table 1: device summary changed title. 09-jul-2007 4 updated table 2: pins descriptions . 09-aug-2007 5 updated table 2: pins descriptions . updated table 12: powersso-24 mechanical data .
l4995 revision history doc id 13103 rev 13 33/35 07-dec-2007 6 updated section 2.2: thermal data : ? corrected note changing single layer with double layer. updated ta bl e 5 : g e n e r a l : ? changed i short typ. value from 750 to 800 ma ? added i short max. value ? changed i lim typ. value from 820 to 900 ma ? added i lim max. value ? added i lim note ? added v dp note ? changed i qn_1 typ. value from 110 to 90 a ? added i qn_1 max. value ? added i qn_50 max. value ? added i qn_150 max. value ? changed i qn_250 typ. value from 1.2 to 1 ma ? added i qn_250 max. value ? changed i qn_500 typ. value from 2.4 to 2.1 ma ? added i qn_500 max. value updated ta bl e 6 : r e s e t : ? changed v rlth parameter definition from ?reset timing low? to ?reset delay circuit low threshold? ? changed v rhth parameter definition from ?reset timing high? to ?reset delay circuit high threshold? ? added t rd min. and max. values updated table 7: watchdog : ? added i wi max value updated table 8: enable : ? changed pull down current symbol from r en to i en ? changed i en typ. value from 2.5 to 10 a ? added i en max. value added section 2.4: electrical characteristics curves . added section 2.5: test circuit and waveforms plot . added section 4: package and pcb thermal data 03-oct-2008 7 updated powersso-24 information: ? changed figure 40: powersso-24 package dimensions ? changed table 12: powersso-24 mechanical data . 19-mar-2009 8 updated table 4: thermal data 19-may-2009 9 updated table 2: pins descriptions . updated figure 4: pins configurations (l4995) ? changed gnd to substrate table 13. document revision history (continued) date revision changes
revision history l4995 34/35 doc id 13103 rev 13 24-jun-2009 10 table 12: powersso-24 mechanical data : ? deleted a (min) value ? changed a (max) value from 2.50 to 2.45 ? changed a2 (max) value from 2.40 to 2.35 ? updated k row ? changed l (min) value from 0.6 to 0.55 ? changed l (max) value from 1 to 0.85 12-jul-2010 11 added figure 27: stability region (1) . 09-mar-2012 12 added footnote in table 3: absolute maximum ratings . 17-oct-2012 13 ta bl e 6 : r e s e t : ?t rd : updated min, typ and max values table 13. document revision history (continued) date revision changes
l4995 doc id 13103 rev 13 35/35 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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